Standard-Cell Tutorials

From VLSIWiki

1. OSU Technology Setup
   
2. Other Technology Setups
   
3. Synopsys Design Compiler (General Synopsys Synthesis Script)
   
4. Advanced Synopsys Design Compiler
   
5. Simulating Verilog
   
6. Cadence Encounter
   
7. Hierarchical Design and Floorplanning
8. Library Modification/Creation

For other tutorials, please see the OSU wiki.